1. Field of the Invention
The present invention relates to image processing devices and related methods for improving image quality, and more particularly, to an image processing device and related method for improving image quality with a Carry-Save-Add (CSA) accumulator.
2. Description of the Prior Art
In digital cameras, digital video cameras, and liquid crystal display (LCD) monitors, color brightness and image stability can be increased by measuring information of original images as a basis for adjustment. Ideally, the information of an entire image would be measured, however insufficient clock speed becomes a problem when gathering the information of the entire image. In the prior art solution, an image is divided into a plurality of frames and a characteristic of each frame is calculated one at a time. This method is effective for static images. However, in dynamic digital video cameras and LCD monitors, a new solution is necessary.
An operating principle of CRT and LCD monitors is generating complete frame control through a horizontal synchronization signal (Hsync) and a vertical synchronization signal (Vsync). An image signal can be produced at an appropriate moment to produce an image on the monitor. Within an image, each frame is produced by an electron gun. After scanning one scan line, the electron gun returns to the beginning of the scan line. Therefore, an image processing device must include a horizontal synchronization signal that tells the electron gun to return after scanning one scan line. After scanning a complete frame, the image processing device outputs the vertical synchronization signal to send the electron gun back to an original vertical position.
Please refer to FIG. 1. FIG. 1 is a diagram of an image processing device for processing image measurement data according to the prior art. After scanning one scan line, the image processing device outputs a horizontal synchronization signal Hsync (the signal Hsync is logic low). After scanning a frame, the image processing device outputs a vertical synchronization signal Vsync (the signal Vsync is logic low). A clock CLK is a signal with a clock period T. During a period of scanning one scan line (the signal Hsync is logic high), the image processing device processes carry-propagate addition (CPA) on image measurement data of a pixel once within the clock period T. A complete addition operation, which includes generating a sum and a carry out, is processed. During a following clock period T, the image processing device processes another complete carry-propagate addition.
Please refer to FIG. 2, which is a diagram of a Carry-Propagate-Adder 22. The Carry-Propagate-Adder 22 includes three inputs. The first input 222 of the Carry-Propagate-Adder 22 is used for receiving a summand A1, the second input 224 is used for receiving a sum input Sin from a preceding Carry-Propagate-Adder, and the third input 226 is used for receiving a carry input Cin from the preceding Carry-Propagate-Adder. The Carry-Propagate-Adder 22 includes two outputs. A first output 228 of the Carry-Propagate-Adder 22 is used for outputting a sum output Sout, and a second output 229 is used for outputting a carry output Cout. The Carry-Propagate-Adder 22 is used for processing addition on data received from the three inputs. A logic operation of the sum output Sout is Sout=A1ΛSinΛCin, which is processing a “NOR” operation on data received from the three inputs. A logic operation of the carry output Cout is Cout=A1Sin|A1Cin|SinCin, which is processing an “AND” operation two-by-two and finally processing an “OR” operation.
In the prior art, the image processing device must process a complete carry-propagate addition within each clock period T, which wastes time. Because current clock speeds are too slow to process image measurement data, an image is divided into several frames to gather information for the whole image. Processing an addition operation on each individual frame and adjusting the individual frames one-by-one leads to poor image quality. If better image quality is required, a complete carry-propagate addition operation must be processed on the image measurement data of the whole image. This improves image quality, but requires more operation time. Therefore, to improve operation speed and to perform more operations within a finite period of time becomes a bottleneck of improving image quality.